Optimization and evaluation of the reconfigurable Grid Alu Processor

Abstract

Currently few architectural approaches propose new paths to raise the performance of conventional sequential instruction streams in the time of the billions transistor era. Many application programs could profit from processors that are able to speed up the execution of sequential applications beyond the performance of current superscalar processors. The Grid Alu Processor (GAP) is a runtime reconfigurable processor designed for the acceleration of a conventional sequential instruction stream without the need of recompilation. It comprises a superscalar processor front-end, a configuration unit, and an array of reconfigurable functional units (FUs), which is fully integrated into the pipeline. The configuration unit maps data dependent and independent instructions simultaneously at runtime into the array of FUs. This paper evaluates the GAP architecture and optimizes the hardware, the number of FUs, and the configuration layers implemented in the array. The simulations show a significant speed up for sequential applications on GAP in comparison to an out-of-order superscalar simulator (SimpleScalar). GAP outperforms SimpleScalar in average by about 50% on the basic architecture and about 100% with an extended version including configuration layers.