Optimistic distributed shared memory

Abstract

Distributed Shared Memory architectures are multiprocessor systems in which each processing node has its own local memory, presenting the programmer with a single linear shared address space spanning the processing nodes. Conventional Distributed Shared Memory architectures provide performance gains through relaxing the memory consistency model at the expense of a complex application programming interface. Programming and achieving good performance on these architectures remains complex for two main reasons. The first is ensuring that concurrent accesses to shared memory locations are synchronized and consistent. The second difficulty occurs in decomposing code into minimally communicating parallel units of execution. This dissertation proposes a new model of computation called Virtual Timestamped Distributed Shared Memory. In this model, memory accesses are timestamped so that a linear temporal order relates all reads and writes according, to program order. This eliminates the need for conventional synchronization primitives such as locks or semaphores while still providing a simple programming model and a sequentially consistent memory. Though different synchronization algorithms could be used to preserve the order of timestamped memory accesses, optimistic TimeWarp synchronization allows memory accesses to execute without restriction and maintains consistency by undoing memory accesses when timestamp order is violated. The perceived benefits for architectures based on the proposed model are numerous. Parallelizing compilers would not need to detect data dependencies, generating threads of execution timestamped to capture the original program order. Substantial speedup was also observed during simulations of standard sequential applications. This dissertation formalizes the Model of Virtual Timestamped Execution which provides the theoretical basis for the Virtual Timestamped Distributed Shared Memory model of computation, and presents an optimistic implementation. Possible architectural designs are presented with the necessary protocol verification. Simulation results of applications running on such architectures are presented together with comparisons to similar work in the literature.