Optimisation in behavioural synthesis using hierarchical expansion: Module ripping

Abstract

During behavioural synthesis, an abstract functional description of a system is mapped automatically onto a physical structure. In a competitive setting, this mapping is highly optimised (the data flow is re-arranged, units and registers are multiplexed and so on) to deliver a final structure that meets some overall user-supplied specification. Ultimately, however, the physical functional units are drawn from a predefined (human-designed) library; these may be thought of as the leaf-level modules in the design hierarchy. Design reuse and increasing sophistication of module libraries inevitably lead to leaf modules becoming larger and more complex. As these modules are, by definition, atomic, a synthesis system is unable to capitalise on any internal similarities the leaf modules may possess. The design, construction and effects of using a hierarchically defined module library are described in the paper. The set of leaf-level modules made available to the synthesis environment is conventional (add, subtract, multiply and so on), but the optimiser is capable of `ripping apart' these modules to manipulate their inner structures. Two advantages accrue from the technique: it is possible to optimise behavioural designs far more effectively, with up to a 65% reduction in area and a 46% reduction in delay; and it is possible to build library modules that have tightly controllable internal timing relationships. This is essential when designing systems that communicate externally via low-level protocols; behavioural synthesis, by its very nature, usually distorts timing information. Using the technique, it is possible to create `islands of fixed timing' embedded in the synthesised design.