Abstract
2.5 D package has been widely used in electronics packages which using multiple integrated circuit chips placed on an interposer to increase its capacity and performance tremendously than traditional 2D package. The lidless package which using heat sink to contact silicon die directly is an effective option to improve the heat dissipation. In this paper, board-level solder fatigue life was investigated for a lidless 2.5D package in accelerated thermal cycling. A three-dimensional finite element model of a lidless 2.5D package with heat sink was studied under various design parameters. Finite element models were built and validated by warpage measurement using 3D DIC system. Coefficient of thermal expansion (CTE) mismatch between different materials is a main factor in warpage controlling. Due to the demand of increasing bandwidth requirements, extension of silicon interposer is necessary. CTE mismatch between the silicon interposer and substrate and between the substrate and PCB are considered. The heat sink is usually bolted to the board. The influence of number of bolts, pre-load force of bolts and location of bolts are performed. It is found that the pre-load force of bolts and CTE of substrate have important impacts on board-level reliability and design suggestions were given.
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