Optimal Thermal Management of Microelectronic Packages

Abstract

The increasing trend in power levels and associated densities leads to the need of design thermal optimization, at module and at system (module-board stack-up) levels. The microelectronics industry is facing multiple challenges as it tries to promote smaller, faster and cost-effective packages, yet trying to cope with potential thermal bottlenecks. The present study investigates a family of packages, whose thermal and electrical performances are far superior to the classic (standard) packages. A 3-D conjugate numerical study was conducted to evaluate the thermal performance of Gallium Arsenic (GaAs) die packaged in Quad Flat No Lead (QFN) packages for various wireless and networking applications. Two different QFN packages are investigated: a standard package and a Power package (PQFN) with thicker leadframe and solder die attach. The thermal impact of die attach material, leadframe thickness, die pad size, and board structure is evaluated and provides valuable information for product designers. Two powering scenarios are investigated: 1) one for standard operating parameters and 2) an alternative for extreme operating powering scenarios. Results indicate that the peak temperature reached on the die for 3x3 mm QFN under normal powering conditions is ~138.5°C (or 119°C/W junction-to-air thermal resistance), while for the extreme scenario, the junction temperature is ~186°C (or 125°C/W junction-to-air thermal resistance). The top Au metal layer has limited impact on lateral heat spreading. Under extreme powering conditions, the PQFN package reaches a peak temperature of ~126°C (66°C/W thermal resistance). A ~32% reduction in peak temperature is achieved with the 5x5 PQFN package. The improvement is mainly due to the larger package size, high conductivity die attach material, thicker leadframe and more board thermal vias. A parametric study shows that the increase in leadframe thickness from 0.2 mm (8 mils) to 0.5 mm (20 mils) in the QFN package leads to only 3% reduction in peak temperature. By comparison, the die attach material (conductive epoxy vs. solder) has significant impact on overall reduction in peak temperature (~12%). Experimental measurements using Infrared (IR) Microscope are performed to validate the numerical results.