Optimal Temperature Regulation of Integrated Circuits with Peltier Heat Pumps

Gilbert De Mey,Krzysztof Górecki,Andrzej Kos

doi:10.3390/en15031125

Gilbert De Mey, Krzysztof Górecki + Show 1 more

Open Access

https://doi.org/10.3390/en15031125

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Journal: Energies	Publication Date: Feb 3, 2022
Citations: 5	License type: CC BY 4.0

Affiliation: Gdynia Maritime University, AGH University of Krakow

Abstract

A thermal network will be presented to model a multi-layer structure consisting of a semiconductor structure, integrated Peltier heat pump and a cooling fin. A criterion will be set up to determine the optimal Peltier current to minimise the chip temperature using the power dissipation as the control parameter. Compared with classical methods, the proposed solution does not show any time delays in response to power changes and is not sensitive to the position of chip temperature sensors. It does not generate chip temperature oscillations. The idea can be applied in each integrated circuit cooled with Peltier heat pumps, e.g., power devices, high-performance processors, high-frequency integrated circuits, etc. The authors present a simple mathematical formula that can be easily implemented in the software of a processor being cooled. As a consequence, the device is able to operate with maximum efficiency assuming required reliability. Theoretical considerations are illustrated by some results of computations. The paper is addressed to designers involved in the creation of devices dissipating a significant amount of heat energy.

Highlights

IntroductionIn CMOS circuits, power consumption depends mostly upon clock frequency
High-performance processors and devices dissipate heat of 300 Watts and more, which requires very efficient cooling systems.In CMOS circuits, power consumption depends mostly upon clock frequency
In CMOS technology of 10 nm and less, power losses consist of two components: the first one is a DC value in a stand-by-state caused by the constant leakage current, and the other is proportional to the clock frequency, which is called the dynamic component

Summary

Introduction

In CMOS circuits, power consumption depends mostly upon clock frequency. In CMOS technology of 10 nm and less, power losses consist of two components: the first one is a DC value in a stand-by-state caused by the constant leakage current (static component), and the other is proportional to the clock frequency, which is called the dynamic component. The higher the clock frequency, the more switching per time unit and the more heat is generated. For the CMOS technology up to 1 μm (e.g., high voltage devices) [1], the leakage current is relatively small, so mostly dynamic heat generation has to be considered. Digital integrated circuits are normally operating at a fixed clock frequency. This basic clock signal being generated by an external quartz crystal oscillator guarantees a very stable frequency. As long as we use data processing by means of electron devices, we have to consider energy losses

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