Optimal Technology Mapping and Cell Merger for Asynchronous Threshold Networks

Abstract

A key challenge in using robust asynchronous circuit styles is the lack of powerful automated optimization techniques. In this paper, optimal technology mapping and cell merger algorithms for robust asynchronous threshold networks are introduced. The technology mapping algorithm is the first systematically to target either delay or area, without destroying the hazard-freedom properties of the initial unoptimized circuits. Both algorithms were implemented and experiments were performed on a near-complete industrial DES circuit provided by Theseus logic, using a particular asynchronous threshold circuit style called NCL (null convention logic), which had been already optimized in a commercial asynchronous synthesis flow based on constrained use of synchronous CAD tools. The average delay improvements for the three largest subcircuits (with over 400 inputs and outputs each) ranged from 20.0-26.7% for technology mapping and 12.6-16.4% for cell merger. When only the single longest path delay of the largest subcircuits is considered, the worst-case delay improvements ranged from 26.0-26.4% for technology mapping and 24.3-26.4% for cell merger. Though the proposed methods are applied in the NCL design flow, the contribution is general enough to be used for other robust asynchronous threshold circuit styles.