Optimal Stress Design in p-MOSFET With Superior Performance

Abstract

It can be shown that pFET high performance can be achieved by ultrahigh compressive stress contact-etching-stop layer (CESL) stressor, embedded SiGe source/drain (S/D) stressor with high Ge concentration, and optimal design of the device dimensions. The optimum design of the device structure results in a suitable 3-D stress distribution in the channel and further has better electric performance for the pFET, in terms of Ion-Ioff enhancement, ballistic efficiency, and injection velocity. In our previous study, multichannel devices with symmetrical W and L (gate width/gate length ratio is < 10) are proposed to enhance the nFET device performance in circuit designs. For pFETs, commonly used wide W inherits uniaxial-like stress, and devices with symmetrical W and L (gate width/gate length ratio is < 10) should be avoided in high-performance circuit designs. The characteristics of the detailed stress simulation and the ballistic transport measurement reported in this brief suggest that these results remain valid for ballistic transport devices with 10-20-nm gate lengths. The pFET stress distribution with different device dimensions was simulated by 3-D finite element mechanical stress simulation, and the mobility, ballistic efficiency, and injection velocity were calculated theoretically and measured based on the stress characteristics. Moreover, the pFET channel stress characteristic from the high-compressive-stress CESL and embedded SiGe S/D stressor has also been further decoupled, and we investigate this effect on the device performance.