Optimal period design of fixed position variable amplitude loop current in FN-PLL for low spurs and fast locking

Abstract

In fixed position variable amplitude loop current based fractional-N phase-locked loop (FN-PLL), reference spurs could be eradicated and fractional spurs are inversely proportional to the period of loop current. Optimal period design of fixed position variable amplitude loop current is proposed for low spurs and fast locking. By using a fix-position variable-period pulse generator, loop current has fixed position, variable amplitude and larger period during locking, in order to eradicate reference spurs and reduce fractional spurs. And, the period of loop current during locking is optimally designed to reduce fractional spurs as far as possible, and realize fast locking by avoiding FN-PLL working back and forth from locking to transient. Spurs and locking time of a FN-PLL are evaluated when reference frequency is 20 MHz and divider ratio is 120.25. Simulation results show the improvement of fractional spurs could be ignored when the period of loop current during locking is more than 27 times larger than the period during transient, but locking time increases from 9.6 μs to a very large value. Thus, the optimal period of loop current during locking is 27 times larger than the period during transient, and so does the design process at the other situations.