Abstract
The RC ladder network has been analyzed for various catastrophic fault detection using minimal number of measurements. Generally, electronic circuit testing procedure is very exhaustive and includes higher cost; the presented approach will save fault diagnosis time. It is not possible to analyze the big RC ladder network to give the good fault coverage, so the ladder network has been broken into segments of different sizes. However, if segment size is small, it will cause more area overhead compared to bigger step size in terms of the interconnections and pins on the integrated circuit. A systematic and detailed analysis for one-step, two-step, three-step, and four-step RC ladder networks has been carried out for various faults and optimal step size is proposed. It has been investigated that three measurements are optimal to localize different catastrophic faults in a RC ladder network.
Highlights
The resistive ladder network has been analyzed for detecting various catastrophic faults associated with it, where only resistive components are considered [1]
The hard faults have been diagnosed using the multiclass classifier and the soft fault is diagnosed using the inverse regression functions. The disadvantage of this method is in resolving the ambiguity; this method uses some auxiliary circuit specific fault diagnosis rules [4]
Kyzioł et al [5] have given an algorithm to diagnose the catastrophic faults in analog circuits
Summary
The resistive ladder network has been analyzed for detecting various catastrophic faults associated with it, where only resistive components are considered [1]. Huang et al have presented an approach based on an assemblage of learning machine that is trained to guide through diagnosis decision It diagnoses the hard/soft fault by using defect filter. Swarm Optimization (PSO); it uses more than one dimension like load resistance and reactance, generator resistance, and reactance and generator frequency to diagnose the faults They have shown that increasing the numbers of dimensions of search space influences the identification of states of circuit under test (CUT). Huang et al [7] have given a method to diagnose the local spot defects in analog circuit This method is based on the combination of multiclass classifiers that are trained using data from fault simulation.
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