Abstract

Friedrichs et al. (TC 2018) showed that metastability can be contained when sorting inputs arising from time-to-digital converters, i.e., measurement values can be correctly sorted without resolving metastability using synchronizers first. However, this work left open whether this can be done by small circuits. We show that this is indeed possible, by providing a circuit that sorts Gray code inputs (possibly containing a metastable bit) and has asymptotically optimal depth and size. Our solution utilizes the parallel prefix computation (PPC) framework (JACM 1980). We improve this construction by bounding its fan-out by an arbitrary $f\geq 3$ f ≥ 3 , without affecting depth and increasing circuit size by a small constant factor only. Thus, we obtain the first PPC circuits with asymptotically optimal size, constant fan-out, and optimal depth. To show that applying the PPC framework to the sorting task is feasible, we prove that the latter can, despite potential metastability, be decomposed such that the core operation is associative. We obtain asymptotically optimal metastability-containing sorting networks. We complement these results with simulations, independently verifying the correctness as well as small size and delay of our circuits. Proofs are omitted in this version; the article with full proofs is provided online at http://arxiv.org/abs/1911.00267 .

Highlights

  • METASTABILITY is a fundamental obstacle when crossing clock domains, potentially resulting in soft errors with critical consequences [14]

  • We demonstrated that efficient metastabilitycontaining sorting circuits are possible

  • Our results indicate that optimized implementations can achieve the same delay as non-containing solutions, without a dramatic increase in circuit size

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Summary

INTRODUCTION

METASTABILITY is a fundamental obstacle when crossing clock domains, potentially resulting in soft errors with critical consequences [14]. BUND ET AL.: OPTIMAL METASTABILITY-CONTAINING SORTING VIA PARALLEL PREFIX COMPUTATION inferring the corresponding output bits. This reduces the design of 2-sortðBÞ to a parallel prefix computation (PPC) problem, which for our purposes can be phrased as follows. We conclude the article, where we briefly discuss follow-up work that generalizes our results, demonstrating that higher-level concepts of this work like sorting networks and parallel prefix computation are applicable to further MC circuits

RELATED WORK
MODEL AND PROBLEM
Binary Reflected Gray Code
Valid Strings
Computational Model and CMOS Logic
DECOMPOSITION OF THE TASK
Dealing with Metastable Inputs
THE PPC FRAMEWORK
The Basic Construction
B À Fdlog BeÀkþ3
Step 1
Step 2
SIMULATION
Results
Comparison to Baseline
CONCLUSIONS
B Circuit
Full Text
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