Optimal fault-tolerant design approach for VLSI array processors

Abstract

A systematic approach for designing a fault-tolerant systolic array using space and/or time redundancy is proposed. The approach is based on a fault-tolerant mapping theory which relates space–time mapping and concurrent error detection techniques. By this design approach, the resulting systolic array is fault tolerant and achieves the optimal space–time product. In addition, it has the capability to compute more problem instances simultaneously without extra cost.