Optimal Design of a Low Power, High Speed One-bit Full Adder Using Multi-Objective Grey Wolf Optimizer

Abstract

The one-bit full adder, as one of the useful electronic circuits, must perform efficiently regarding power consumption and delay time. In this paper, the multi-objective grey wolf optimizer is used to optimize one of the latest hardware designed for a one-bit full adder. By optimizing the MOSFET channel width in TSMC 0.18 μm technology, the performance of the circuit has improved significantly in terms of minimizing power consumption and delay time compared to the original version. The prove the efficiency of the proposed method, experimental results are compared with other meta-heuristic methods such as multi-objective particle swarm optimization (MOPSO) and non-dominated sorting genetic algorithm II (NSGA-II). Results show that employing meta-heuristics to optimize the performance of the one-bit full adder is an effective approach to reduce power consumption and delay time. In addition, MOGWO leads to competitive and in some experiments better results compared to MOPSO and NSGA-II.