Optimal Design of a Half-Wave Cockcroft–Walton Voltage Multiplier With Minimum Total Capacitance

Abstract

Even though the half-wave Cockcroft-Walton voltage multiplier (H-W C-W VM) is one of the most common ac-dc step-up topologies, VM designers tend to use equal capacitances in every stage, a fact that leads to a nonoptimal design. The aim of this paper is to introduce a new design method of H-W C-W VM that lays on the calculation of the optimal number of stages, which is necessary to produce the desired output voltage with the minimum total capacitance value. For this purpose, an adequate choice of the capacitance values per stage is considered, leading to the investigation of four different cases. The theoretical analysis is validated by PSPICE simulations and experimental results, accomplished on laboratory prototypes.