Optimal Arrangement of Multiple Heat Sources in Vertically Stacked Two-Layer 3-D IC Using Genetic Algorithm

Abstract

Abstract The semiconductor packaging technologies have seen its growth from MCM (Multi-chip module), SiP (System in Package), SoC (System on Chip) to the heterogeneous integration of the MCM. Thermal management of multi-chip vertically integrated systems poses additional constraints and limitations beyond those for single chip modules. 3-D integrated circuits (3-D ICs) technology is a potential approach for next-generation semiconductor packaging technologies. A 3-D IC is formed by vertical interconnection of multiple substrates containing active devices which offer reduced die footprint and interconnect length. This manuscript discusses the optimal arrangement of two hotspots on each layer of a two-die stacked 3-D IC. An analytical heat transfer model for prediction of three-dimensional temperature field of a 3-D IC based on the solution of governing energy equations has been developed and used for this study. The model is subject to adiabatic boundary conditions at the walls except for the bottom wall which is subject to convective boundary condition. Genetic Algorithm is employed for solving two non-conflicting objectives constrained optimization problem. The first objective aims to minimize the maximum temperature on both layers, the second objective aims to achieve temperature uniformity in the layers. A feed-forward back propagation Artificial Neural Network (ANN) is employed for obtaining the functional relationship between the location of the hotspots and the objectives. The results of the optimization study are expected to provide recommendations on the design guidelines for arranging hotspots on vertically stacked substrates.