Optimal address register allocation for arrays in DSP applications

Abstract

Optimizing the code size of a digital signal processing application is a crucial step in generating high quality and efficient code for embedded systems. Most modern digital signal processors (DSPs) provide multiple address registers and a dedicated address generation unit (AGU) that provides address generation in parallel to instruction execution. There is no address computation overhead if the next address is within the auto-modify range. Many DSP algorithms have an iterative pattern of references to array elements within loops. Thus, a careful assignment of array references to address registers reduces the number of explicit address register instructions as well as the execution cycles. In this paper, we present an optimal integer linear programming (ILP) formulation for the address register allocation problem (ARA) with code reconstructing techniques. Genetic algorithm is also used to solve the ARA problem to get a near-optimal solution in a reasonable amount of time for big embedded applications. Results on several benchmarks show the effectiveness of our techniques compared to other techniques in the literature.