Abstract
In this paper a novel opto-electronic Track-and-Hold Amplifier (OE-THA) is presented. The OE-THA can be used as a sampler in a photonic analog-to-digital-converter (ADC). It is fabricated in a silicon photonic 250 nm SiGe BiCMOS technology to allow for monolithic integration of photonic and electronic components. The OE-THA chip exhibits a small signal bandwidth of over 65 GHz, a total harmonic distortion below -34 dB up to 75 GHz and a signal-to-noise and distortion ratio (SINAD) of over 35 dB (5.5 effective bits, ENOB) up to 45 GHz. The measured resolution bandwidth products result in a corresponding equivalent jitter of below 80 fs rms from 20 to 70 GHz. The best equivalent jitter is achieved at 41 GHz with a value of 55.8 fs rms. This is enabled by using a low-jitter optical pulse train, generated by a Mode-Locked-Laser (MLL), as an optical sampling clock. The circuit integrates all optical and electronic components besides the MLL. It draws 110 mA operated from a supply voltage of -4.6 V and occupies a silicon area of only 0.59 mm2.
Highlights
In digital communication systems as well as high-end measurement equipment broadband ADCs play an important role
It can be divided into six components: the photonic frontend, 50 Ω analog input stage (InBuf), main amplifier (MA), switched-emitter-follower (SEF), output buffer (Out), and 50 Ω test buffer (Test)
We present schematic and layout level design and measurement results of a novel opto-electronic sampler: the optically clocked switched-emitter-follower track-and-hold amplifier
Summary
In digital communication systems as well as high-end measurement equipment broadband ADCs play an important role. State-of-the-art ultra-broadband ADCs implemented in CMOS technologies are mostly based on time-interleaving (TI) and use large numbers of low-power, low-speed sub-ADCs in parallel In this way very high sampling rates of more than 100 GS/s and moderate power dissipation have been achieved. Compared to electronic clocks the envelope of an optical pulse train generated by a mode-locked laser (MLL) can achieve an RMS timing-jitter in the attosecond region [3,4] This has led to research into photonic samplers and ADCs where the sampling clock is provided by a low-jitter MLL [5,6,7,8]. It was shown that the OE-SEF provides a higher bandwidth than MZM-based samplers in state-of-the-art silicon photonic technologies and achieves a high linearity without need for digital post processing.
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