Optical proximity correction for 0.3 μm i-line lithography

Abstract

In printing random logic circuits down to 0.3 μm using i-line lithography, optical proximity correction is required to maintain across-the-chip linewidth uniformity. Using a rule-based approach with parametric anchoring, process characterization time is kept to a minimum. Corrections are more effective if post-OPC design grid sizes are kept small (∼5 nm at 1X).