Abstract

TileCal is the central hadronic calorimeter of the ATLAS experiment at the Large Hadron Collider (LHC). It is a sampling detector where scintillating tiles are embedded in steel absorber plates. The tiles are grouped forming cells, which are read-out on both sides by photomultiplier tubes (PMTs). The PMT digital samples are transmitted to the Read-Out Drivers (ROD) located in the back-end system for the events accepted by the Level 1 trigger system. The ROD is the core element of the back-end electronics and it represents the interface between the front-end electronics and the ATLAS overall Data AcQuisition (DAQ) system. It is responsible for energy and time reconstruction, trigger and data synchronization, busy handling, data integrity checking and lossless data compression. The TileCal ROD is a standard 9U VME board equipped with DSP based Processing Units mezzanine cards. A total of 32 ROD modules are required to read-out the entire TileCal detector. Each ROD module has to process the data from up to 360 PMTs in real time in less than 10 microseconds. The commissioning of the RODs was completed in 2008 before the first LHC collisions. Since then, several hardware and firmware updates have been implemented to accommodate the RODs to the evolving ATLAS Trigger and DAQ conditions adjusted to follow the LHC parameters. The initial ROD system, the different updates implemented and the operational experience during the LHC Run 1 and Run 2 are presented.

Highlights

  • Luminosity L ~ k· N2/ Seff k : Number of bunches N : bunch population Seff : effective collision cross-section

  • + Data requested from ROBs over network + Full detector granularity in Region of Interest (RoI)

  • ❅ ROD configuration: § 2 Processing Units per ROD : 90 PMTs data processed on each DSP § Input : raw data à output: OF reco and complete raw data § OF iterative : good performance in absence of pileup

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Summary

TileCal ReadOut Drivers

Read-Out Drivers – interface between the front-end electronics and the High Level Trigger. ❅ Deserialization, data/trigger synchronization, error checking, signal reconstruction, detector raw data compression, output data formating, monitoring, data flow control (veto). ❅ Data routing and formatting in FPGAs (VHDL), data processing in DSP (C & assembler)

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Jul Oct Month in Year
ROD firmware and software updated
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