Abstract
A design methodology is described for analog circuits in which topological design is followed by simultaneous device sizing and layout design. By merging circuit and layout design into a single design process, analog circuits can be optimally designed, taking layout parasitics fully into account. Based on the methodology, a CMOS operational amplifier compiler (OAC) has been developed. Given a set of performance specifications and process parameters, OAC generates a layout with circuit performance optimized to meet specified performance constraints. A novel procedural layout technique is used for generating compact and practical layouts. A nonlinear optimization method is applied for device sizing that relies on the results of simulations based on the circuit extracted from the layout. Design experiments have shown that OAC can produce satisfactory results with respect to both circuit performance and layout density
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