Abstract
Current mirrors (CMs) are essential building blocks for biasing electronic circuits. The present work demonstrates that errors in mirroring ratios increase at cryogenic temperatures, for all types of SiGe HBT and CMOS CMs. The sources of errors are attributed to the mismatch in operating conditions and a combination of process variations and layout effects. In particular, the effects of layout on device current are found to increase significantly at low temperatures, which can potentially contribute more to the CM error than process variations. Among all investigated CM configurations, the simple CM based on large geometry SiGe HBTs is the most versatile option with small errors, a large operational range, and a simple layout.
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