Operation Characteristics of Gate-All-Around Junctionless Flash Memory Devices With Si₃N₄/ZrO-Based Stacked Trapping Layer

Abstract

The operation characteristics of polycrystalline Si (poly-Si) gate-all-around (GAA) junctionless (JL) charge-trapping (CT) flash memory devices with the Zr-based stacked trapping layer were studied in this work. Devices with the Si3N4/ZrO2 stacked trapping layer show enhanced erasing speeds and comparable retention characteristics in comparison to Si3N4/HfO2 due to many shallow energy traps and smaller valance band offset in the ZrO2 layer. By inserting Al2O3 between Si3N4 and ZrO2 trapping layer, the retention and endurance characteristics are improved. The erasing speed can be further improved by a Zr-rich oxide layer near the tunneling oxide since the energy barrier can confine more injected electrons near the tunneling oxide. The retention characteristic can be improved without sacrificing the erasing speed because some of the shallow traps can be passivated by NH3 plasma treatment on ZrO2. Hence, the ZrO-based stacked trapping layer is very promising for the poly-Si GAA JL CT flash devices for nonvolatile memory applications.