Open loop sigma-delta modulators for digital-to-analog converters with high speed improving using time interleaving

Abstract

Sigma-delta (SD) modulator based DACs are simple circuits with low accuracy requirements in their analog components. However, their signal bandwidth is limited by speed constrains. In this respect, Time-Interleaving (TI) allows the designer to trade-off between complexity and speed by replacing the original architecture by N parallel paths clocked at a frequency N times smaller. Unfortunately, this is only possible for small values of N because the resulting TI architecture has long combinatorial paths. These paths reduce the maximum clock rate. In closed-loop SD architectures these paths cannot be broken by the insertion of registers, because an increase of the loop delay compromises the stability of the modulator. This paper proposes a TI decomposition in open-loop SD modulators, which allows the insertion of as many registers as desired to shorten the critical combinatorial path. Consequently, the clock frequency (and, hence, the performances) can be increased at its maximum. The proposed method is illustrated with a second-order modulator, which has been synthesized in an FPGA (Spartan-6 xc6slx75t). Post-route static timing analysis and simulations show a considerable increase of performances. In authorś knowledge, it is the first time that TI is applied in open-loop SD modulators, resulting in very speed DACs.