ONO and Tunnel Oxide Characterization and Optimization for High Speed EEPROM Device

Abstract

Non-volatile memory processes, in particular the EEPROM process, is one of the hardest processes to be developed and the performance of the NVM products is normally judged from the programming speed and the density of the memory. The programming speed of the EEPROM cell depends critically on Tunnel Oxide Thickness (Xtun), Programming Voltage (Vp), ONO Thickness (Xpp) and Poly to Poly overlap Area (App). However, in this experiment only ONO and tunnel oxide layer are optimized and characterized. Three experiments were setup to improve the programming speed. The first experiment was to scale down the ONO layer thickness and followed by measurement of the threshold voltage and breakdown voltage of the new ONO thickness. The second and third experiments were setup to check the integrity of ONO and tunnel oxide layers respectively. The EEPROM cell was fabricated to observe the cross sectional of ONO and tunnel oxide layer. The characterization work on ONO and tunnel oxide layer to increase the programming speed of the memory cells of a 16k EEPROM device has been carried out. After scaling down the nitride of ONO layer from 160_ to 130_, the Vt program windows are further improved from 4.3V to 4.5V and from 0.7V to 0.9V for program high and program low operations, respectively. In this experiment, 130_ was found to be the best thickness for nitride of ONO layer. The breakdown voltage for ONO at 130_ of nitride thickness is 16.3V. The experiment revealed that the yields of ONO and tunnel oxide layer of the actual size on silicon were achieved at 98.7% and 99.92%, respectively. Key words: ONO; tunnel oxide; EEPROM; threshold voltage; programming speed; polysilicon; control gate; floating gate; select gate