Abstract
The authors propose a testable design of random access memories (RAM) which facilitates both on-line and off-line testing of the devices. The high density of the memory devices necessitates high speed off-line testing techniques. Critical applications desire on-line testability of these devices. The proposed design partitions the chip into blocks and sets in order to achieve high speed off-line testability as well as on-line testability. >
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.