One step forward from run-to-run critical dimension control: Across-wafer level critical dimension control through lithography and etch process

Abstract

Process variation on lot-to-lot and wafer-to-wafer level has been well addressed using run-to-run control in advanced process control, however, to tackle the ever increasing die-to-die level process variation at the 65 nm technology and beyond, the process control must be extended into finer domain: die-to-die level. A novel model based process control approach is proposed to reduce the critical dimension(CD) variation on die-to-die level, i.e. across-wafer level. The central idea of the proposed approach is to compensate for upstream and downstream systematic CD variation by adjusting the across-wafer post-exposure bake (PEB) temperature profile of a multi-zone bake plate. A temperature-to-offset model relating the PEB temperature profile of multi-zone bake plate to its heater zone offsets was constructed experimentally using wireless temperature sensors from OnWafer Technologies. The baseline post-etch CD signature and plasma etch bias signature were extracted from the characterization experiment. A post-etch CD variation reduction of 40% was realized in the verification experiment, which validated the efficacy of the proposed approach. This CD variation control concept was further extended to simultaneous CD variation control for multiple CD features considering that multiple CD features coexist on a real chip, and CD variation control scheme based on multi-objective and minimax optimization is proposed to realize simultaneous CD variation control for multiple CD features. We also demonstrate through simulation using minimax optimization that across-wafer CD variation of multiple CD features can be significantly reduced for the 130 nm technology node and beyond.