One Dimensional SIMD Array Processor with Segmentable Bus

Abstract

By the analysis of the application requirement and the architectures of parallel computer, an embedded data parallel computer architecture model is proposed for multimedia processing applications. In the proposed model, local memory based on PIM technology reduces memory latency and increases bandwidth. Additionally, segmentable bus provides high flexibility for different demands so that PEs can cooperate with each other more efficiently. The main components and the instruction set were described in detail. A typical algorithm example is given to show the process of parallel computation. And we are implementing this model under Xilinx FPGA board.