Abstract
Power supplies in portable applications must not only conform and adapt to their highly integrated on-chip and in-package environments but also, more intrinsically, respond quickly to fast load dumps to achieve and maintain high accuracy. The frequency-compensation network, however, limits speed and regulation performance because it must cater to all combinations of filter capacitor , inductor L, and 's equivalent series resistance resulting from tolerance and modal design targets. As such, it must compensate the worst-case condition and therefore restrain the performance of all other possible scenarios, even if the likelihood of occurrence of the latter is considerably high and the former substantially low. Sigma-delta () control, which addresses this issue in buck converters by easing its compensation requirements and offering one-cycle transient response, has not been able to simultaneously achieve high bandwidth, high accuracy, and wide compliance in boost converters. This paper presents a dual-mode boost bypass converter, which by using a high-bandwidth bypass path only during transient load-dump events was experimentally 1.41 to 6 times faster than the state of the art in current-mode boost supplies, and this without any compromise in compliance range (0–50 m, 1–30 H, and 1–350 F).
Highlights
In portable applications like cellular phones, PDAs, and the like, integrated BiCMOS and CMOS switching dc-dc supply circuits reduce cost, size, component count, and design complexity
This paper presents a dual-mode boost ΣΔ bypass controller integrated circuits (ICs) that overcomes the aforementioned speedstability compromise by introducing a high-speed bypass mode that engages only during transient loaddump events, achieving both high bandwidth and wide RESRLC compliance
Currentsense amplifier ADI, which monitors the voltage across RI, includes an internal RC filter that generates differential current reference vI.REF
Summary
In portable applications like cellular phones, PDAs, and the like, integrated BiCMOS and CMOS switching dc-dc supply circuits reduce cost, size, component count, and design complexity (from a user’s perspective). In realizing ΣΔ control in boost converters, the feedback circuit must explicitly sense and mix inductor current with the sensed output voltage [9] Such techniques, resurrect the limiting speed-stability tradeoffs ΣΔ control averted in buck converters in the first place, forcing the designer to adjust current and voltage gains thereby reducing the loop bandwidth in order to accommodate large RESR LC filter values. This paper presents a dual-mode boost ΣΔ bypass controller IC that overcomes the aforementioned speedstability compromise by introducing a high-speed bypass mode (and circuit) that engages only during transient loaddump events, achieving both high bandwidth and wide RESRLC compliance
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