On-die 16nm metal critical peak current test methodology with 100ps pulse width

Abstract

A new methodology to measure the product-like AC stress of metal critical peak current was implemented in 16nm High-K Metal Gate (HKMG) FINFET process. Traditional TLP tester can only generate minimum 1ns pulse width stress, which is still in thermal diffusion metal burn out regime. The proposed method can generate minimum pulse width of 100ps stress waveform through on-die tunable pulse-width generator and time-to-current duty detector circuits. The silicon data first demonstrated Cu critical peak current will enter the adiabatic regime under 100ps pulse width with 10X peak current than in thermal diffusion regime. This wafer-level measurable test vehicle can be put on scribe-line as Design-For-Manufacturing (DFM) DC-to-AC metal reliability monitor system.