On-Demand Fabrication of Si/SiO2 Nanowire Arrays by Nanosphere Lithography and Subsequent Thermal Oxidation

Huaxiang Cao,Bukang Zhou,Tao Chen,Tongfei Shi,Yuqi Wang,Xinhua Li,Jianqiang Zheng,Guangqiang Liu

doi:10.1186/s11671-017-1883-5

Abstract

We demonstrate the fabrication of the large-area arrays of vertically aligned Si/SiO2 nanowires with full tunability of the geometry of the single nanowires by the metal-assisted chemical etching technique and the following thermal oxidation process. To fabricate the geometry controllable Si/SiO2 nanowire (NW) arrays, two critical issues relating with the size control of polystyrene reduction and oxide thickness evolution are investigated. Through analyzing the morphology evolutions of polystyrene particles, we give a quantitative description on the diameter variations of polystyrene particles with the etching time of plasma etching. Based on this, pure Si NW arrays with controllable geometry are generated. Then the oxide dynamic of Si NW is analyzed by the extended Deal-Grove model. By control, the initial Si NWs and the thermal oxidation time, the well-aligned Si/SiO2 composite NW arrays with controllable geometry are obtained.

Highlights

Due to their unique chemical, optical, and electrical properties, Silicon nanowire (Si NW) structures are the important bases of the generation of high efficiency and low-cost electronic devices [1,2,3,4,5]
Before realizing the fabrication of Si/ SiO2 NW arrays, it is necessary to prepare pure Si NW arrays with well-controlled geometry by Metal-assisted chemical etching (MACE) combined with nanosphere lithography (NSL)
In conclusion, large-scale and deterministic assembly of Si/ SiO2 NW arrays are realized by the MACE combined with the following thermal oxidization process

Summary

Introduction

Due to their unique chemical, optical, and electrical properties, Silicon nanowire (Si NW) structures are the important bases of the generation of high efficiency and low-cost electronic devices [1,2,3,4,5]. By reference to the documents on the fabrication of pure Si NW arrays, one can find numerous methods that have been developed to fabricate Si nanostructure by using bottom-up or top-down approaches, such as vapor-liquidsolid (VLS) growth [16, 17], reactive ion etching [18], or electrochemical etching [19].

Methods

Results

Conclusion