On-Current Modeling of Polycrystalline Silicon Thin-Film Transistors

Abstract

We propose an on-current (above threshold voltage) model of polycrystalline silicon thin-film transistors (poly-Si TFTs). The model includes the study of the effect of trap state density, poly-Si inversion layer thickness and temperature on the TFT characteristics. Effective carrier mobility and I-V characteristics are described by considering the mechanism of capture and release of carriers at grain boundary trap states and the thermionic emission theory. It is found that at low as well as at high doping concentrations, the effective carrier mobility (µeff) increases with increasing temperature whereas a dip is observed at intermediate doping concentration. At very high and very low doping concentration the effect of temperature on the mobility is found to be almost negligible. Calculations reveal that effective carrier mobility and drain current increase as the gate bias increases and are larger for a lower trap state density. The calculated value of activation energy decreases as the gate bias increases and is larger for a larger poly-Si inversion layer thickness. A comparison between the present predictions and the experimental results shows reasonably good agreement.