On‐chip triplexer using series‐first structure for connecting radio frequency modules in a 65 nm CMOS

Abstract

AbstractIn this study, we implemented a triplexer using a 65‐nm CMOS process. The triplexer was composed of a low‐pass filter (LPF), bandpass filter (BPF), and high‐pass filter (HPF). Each filter was designed with a Chebyshev structure to obtain a sharp skirt characteristic and series‐first structure to achieve impedance matching in a common terminal, reduction of insertion loss and compact size. The proposed triplexer operates at 0–2 GHz, 5.8–6.5 GHz, and 10.7–14 GHz. In addition, the triplexer shows that the return loss of all ports is more than 10 dB in the bandwidth used. The insertion losses in the passbands, LPF, BPF, and HPF were less than 2.5, 5.55, and 4.4 dB, respectively. The attenuation levels in the stopbands of the LPF, BPF, and HPF are over 47.6, 33.6, and 43.7 dB, respectively. The active area of the triplexer is 0.7 mm × 0.67 mm. To our knowledge, this circuit is the first implementation of a CMOS on‐chip triplexer.