On-Chip Power Grids with Multiple Supply Voltages

Abstract

With the on-going miniaturization of integrated circuit feature size, the design of power and ground distribution networks has become a challenging task. With technology scaling, the requirements placed on the on-chip power distribution system have significantly increased. These challenges arise from shorter rise/fall times, lower noise margins, higher currents, and increased current densities. Furthermore, the power supply voltage has decreased to lower dynamic power dissipation. A greater number of transistors increases the total current drawn from the power supply. Simultaneously, the higher switching speed of a greater number of smaller transistors produces faster and larger current transients in the power distribution network [286]. The higher currents produce large IR voltage drops. Fast current transients lead to large L dI∕dt inductive voltage drops (\(\Delta I\) noise) within the power distribution networks.