Abstract
Thermal management of microprocessors has become an increasing challenge in recent years because of localized high flux hot spots which cannot be effectively removed by conventional cooling techniques. This paper describes the use of the silicon chip itself as a thermoelectric cooler to suppress the hot spot temperature. A three-dimensional analytical thermal model of the silicon chip, including localized thermoelectric cooling, thermoelectric heating, silicon Joule heating, hot spot heating, background heating, and conductive/convective cooling on the back of the silicon chip, is developed and used to predict the on-chip hot spot cooling performance. The effects of hot spot size, hot spot heat flux, silicon chip thickness, microcooler size, doping concentration in the silicon, and parasitic Joule heating from electric contact resistance on the cooling of on-chip hot spots, are investigated in detail.
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