On-chip high-voltage SPAD bias generation using a dual-mode, closed-loop charge pump

Abstract

Single-photon avalanche diodes (SPAD) are high sensitivity photon detectors used in time-resolved imaging and very low-light applications. Operation as an avalanche detector requires reverse bias beyond the breakdown voltage, which is typically much higher than supported voltages in a standard CMOS process. In order to realize a fully integrated photon detection system using SPAD devices, this high-voltage bias needs to be generated on chip. Generated voltages beyond the breakdown threshold of the process pose particular design challenges, especially for output sampling and closed-loop regulation. This paper presents design and architectural techniques used to implement a closed-loop DC-DC converter that can be fully integrated on-chip and produces a regulated output voltage exceeding 15 V. Particular design constraints imposed by high on-chip voltages are addressed, and presented simulation results are based on an implemented design in a standard 130 nm CMOS process. The charge pump generates an output voltage of 15 V in 2 μs from start, with a modeled SPAD load of 10 pF. Following an avalanche current pulse, the recovery transient time is <150 ns to settle within 140 mV of the desired output voltage.