On-chip dynamic programming networks using 3D-TSV integration

Abstract

Recent technological advances in three-dimensional (3D) semiconductor fabrication have provided a promising platform for realizing densely interconnected multicore, multiprocessor, and networks-on-chip (NoC) based systems. As the on-chip complexity grows significantly with the number of computational, control, and communication units, design considerations and the provision for efficient run-time resources management in large-scale system becomes critical. We have developed an on-chip distributed dynamic-programming (DP) network [3] [5] for a range of applications including optimal paths planning [6], dynamic routing [5] and deadlock detection [2]. This paper presents a design of DP-network, implemented in a fully stacked 3-layer three-dimensional (3D) through-silicon via (TSV) 150 nm CMOS technology through MIT Lincoln Lab [1]. The vertical inter-unit communication is achieved by means of TSV, and the mesh interconnection provides a natural minimal area overhead associated with this communication. The prototype circuit measures 2mm×2mm. Test results demonstrated the effectiveness of such a DP-network for deadlock detection and the computational delay is less than 9 ns for detecting deadlock from a large-scale network. This work provides promising results for future networks-on-chip application using 3D embedded DP-network.