On-chip data communication : analysis, optimization and circuit design

Abstract

On-chip data communication is an active research area, as interconnects are rapidly becoming a speed, power and reliability bottleneck for digital CMOS systems. Especially for global interconnects that have to span large parts of a chip, there is an increasing gap between transistor speed and interconnect bandwidth. To alleviate this problem, improvements in technology, architectures and circuits are needed. On the technology side, low-k dielectrics and reverse scaling can improve the interconnect behavior. On the architecture side, Network on chips (NoCs) can reduce the number of global interconnects. On the circuit side, which is the focus area of this thesis, more advanced strategies than the classical repeater insertion can be used to reduce the power consumption and increase the communication speed. In the thesis, it is shown that the bandwidth of interconnects is either limited by their distributed RC behavior (for long interconnects), or by the skin-effect. In both cases, the bandwidth is proportional to the cross-sectional area and inversely proportional to the length squared. The aggregate bandwidth per cross-sectional area can be optimized by choosing all cross-sectional dimensions roughly equal. The bandwidth of a single interconnect can be increased by using resistive (or resistive-inductive) receiver termination or capacitive transmitter termination. The crosstalk can be mitigated with twisted differential interconnects, where the number of twists determines for how many neighbors the crosstalk can be cancelled. With the aid of a symbol response analysis method, it is shown that simple equalization schemes are very effective to boost the achievable data rate, more so than multi-level signaling or band-pass modulation. To validate the concepts two demonstrator ICs were developed, both using 10mm long interconnects. The first chip, in a 130nm CMOS process, showed that a combination of pulse-width pre-emphasis, twisted interconnects and low-ohmic receiver termination can boost the data rate to 3Gb/s/ch (at 2pJ/bit), while a conventional transceiver reached only 0.55Gb/s/ch. The second test-chip, in 90nm CMOS, showed that a combination of a capacitive transmitter and a low-power sense-amplifier with DFE at the receiver can reduce the energy consumption to 0.28pJ/bit (at 2Gb/s), much lower than competing designs. Circuit simulations show that a capacitive transmitter and a low-power sense amplifier can also be very effective as transceivers in a NoC, with data rates in excess of 9Gb/s (at 130fJ/transition) over 2mm interconnects. Multiple transceivers can be connected back-toback to create a source-synchronous transceiver-chain with a wave-pipelined clock, operating with 6σ offset reliability at 5 Gb/s