On V–V/V–I type double balanced CMOS multiplier utilizing triode-region translinear principle

Abstract

For the first time, the triode-region of MOSFET has been exploited to evolve a novel technique in which voltage-translinear loop expression has been converted into voltage multiplication expression. This expression is thus utilized in realizing a triode-region translinear principle-based fully differential, four-quadrant CMOS voltage-to-voltage and voltage-to-current type multipliers. The elaborate CMOS design approach has been given and the second-order effects have been considered on its performance. The workability of the proposition has been verified by Spectre tool of Virtuoso from Cadence using 180 nM GPDK parameters by performing post layout simulation.