Abstract

A Software Defined Radio for Ultra Wideband (UWB) communication systems places several stringent requirements on the Analog-to-Digital Converter (ADC). In particular, the ADC must have sufficiently high sampling frequency?typically ypically on the order of several gigasamples per second?to accurately reconstruct the received UWB pulse. An alternative approach to using a single expensive ADC with the above features is to sample the received signal with an array of lower speed ADCs driven by time-interleaved (TI) sampling clocks, allowing the array to operate as if it were a single ADC with a much higher effective sampling frequency. However, ADC timing, gain and offset mismatches represent significant design challenges in such architectures. In this paper, we investigate the use of a pilot-based matched-filter architecture in mitigating the impact of ADC gain, offset, and timing mismatches. The analytical results derived in this paper (a) demonstrate the efficacy of a pilot-based matched filter in mitigating the impact of timing mismatch errors on a TI-ADC array, and (b) allow for the design specification of the number of pilots required in order to achieve desired system performance.

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