On the Thermal Dissipation of the Board-Level Electronic Packaging

Abstract

Nowadays, thermal management for semiconductor devices has become critical. A poor thermal management and design in a high power electronic device may result in a significant chip junction temperature and considerable temperature gradient among components within a package. Mulgaonker et al.[l] indicated that in a typical design guideline, the temperature of chips could not exceed 105°C and that of PCB should be less than 90°C. Thus, the main objective of this work is to study the heat dissipation mechanism of the board-level Plastic Ball Grid Array (PBGA) electronic packaging (Fig. l(a)) in a steady state under a natural convection environment based on JEDEC specification [2, 3, 4, 5]. To achieve the goal, theoretical characterization that integrates a detailed three-dimensional finite element modeling technique (Ellison[6]) is proposed. The validity of the proposed theoretical characterization is confirmed in terms of chip junction temperature as well as junction-to-ambient (J/A) thermal resistance through an effective infrared(IR)-thermography-based thermal characterization technique (Fig. l(b)) and thermal test die measurement (Chen et al.[7]). To perform surface temperature measurement (Fig. 2(a)) using an IR thermometer, the black paint coating is applied on the surface of packages so as to calibrate the surface radiation. The associated emissivity is approximately assessed using a simple calibration experiment, and besides, an appropriate thickness of the coating is determined. Moreover, to demonstrate the accuracy of the thermal test die measurement, the uncertainty analysis is also performed. Based on the validated theoretical model, the influences of various design parameters of the PCB structure on the thermal performance are studied.