On the SiO/sub 2/-based gate-dielectric scaling limit for low-standby power applications in the context of a 0.13 μm CMOS logic technology

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This paper describes a leading-edge 0.13 /spl mu/m low-leakage CMOS logic technology. To achieve competitive off-state leakage current (I/sub off/) and gate delay (T/sub d/) performance at operating voltages (V/sub cc/) of 1.5 V and 1.2 V, devices with 0.11 /spl mu/m nominal gate length (L/sub g-nom/) and various gate-oxide thicknesses (T/sub ox/) were fabricated and studied. The results show that low power and memory applications are limited to oxides not thinner than 21.4 /spl Aring/ in order to keep acceptable off-state power consumption at V/sub cc/=1.2 V. Specifically, two different device designs are introduced here. One design named LP (T/sub ox/=26 /spl Aring/) is targeted for V/sub cc/=1.5 V with worst case I/sub off/ <10 pA//spl mu/m and nominal gate delay 24 ps/gate. Another design, named LP1 (T/sub ox/=22 /spl Aring/) is targeted for V/sub cc/=1.2 V with worst case I/sub off/<20 pA//spl mu/m and nominal gate delay 27 ps/gate. This work demonstrates n/pMOSFETs with excellent 520/210 and 390/160 /spl mu/A//spl mu/m nominal drive currents at V/sub cc/ for LP and LP1, respectively. Process capability for low-power applications is demonstrated using a CMOS 6T-SRAM with 2.43 /spl mu/m/sup 2/ cell size. In addition, intrinsic gate-oxide TDDB tests of LP1 (T/sub ox/=22 /spl Aring/) demonstrate that gate oxide reliability far exceeding 10 years is achieved for both n/pMOSFETs at T=125/spl deg/C and V/sub cc/=1.5 V.