On the reduction of direct tunneling leakage through ultrathin gate oxides by a one-dimensional Schrödinger–Poisson solver

Abstract

A full self-consistent one-dimensional Schrödinger–Poisson model is reported in this article, which is specifically dedicated to the study of direct tunneling current through ultrathin gate oxide of metal-oxide-semiconductor (MOS) structures. The gate current is obtained by estimating the quasibound state lifetimes within the formalism of the formal reflection delay time of wave packets using the transfer-matrix method. As an alternative design to conventional MOS structures, two strategies are investigated in this work to scale oxide thickness in the sub 1.5 nm range while keeping an acceptable gate current leakage of some A/cm2. These include nitride/oxide stacked gate dielectrics used to increase the insulator thickness, and heterostructure MOS capacitors to confine electrons in a buried quantum well. Tensile strained Si1−yCy/Si and Si/Si1−xGex heterostructures that provide a convenient conduction band offset are proposed in this order. A conduction band offset of 0.19 eV is shown to yield nearly the same but limited improvement than the stacked gate dielectrics structure. Compared with the conventional MOS device of equivalent oxide thickness, a gate current reduction by more than two orders of magnitude is reached by using a heterostructure with a conduction band offset of 0.31 eV. For MOS transistor application this significant gain may be in addition to the driving current increase that can be expected from the strain-induced improvement of electron transport properties.