Abstract
A procedure for testing the realizability of complete 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</sup> -state directed graphs by means of n-stage synchronous autonomous sequential networks of particular types, supplying at the same time state assignments pertaining to realizations of a specified class, is described. The analysis is confined to decomposed and linear networks, although the outlined method, based on the matrix representation of sequential circuits, can be applied to other types of networks. The similarity between transition matrices and corresponding logic matrices permits deriving circuit results through sole consideration of state graph structures. By resorting to the classical theory of rational canonical matrices, with any transition matrix a unique set of invariant vector subspaces of the 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</sup> -dimensional space is systematically associated, upon which the prescribed realizability test is performed.
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