On the processing aspects of high performance hybrid backside illuminated CMOS imagers

Abstract

In this paper we present a successful integration scheme of a backside (BS) illuminated 1024 × 1024 pixel, 30 µm thin, sensor array that is flip chipped on a read-out IC die with 10 µm diameter indium micro bumps, where the pixel pitch is 22.5 µm. A novel BS alignment strategy to avoid Pyrex glass as a temporary carrier for wafer thinning is described. Pyrex is namely not compatible in a high-end Si process environment due to its fragile and contaminating nature. Further special attention is given to critical steps leading toward high broadband quantum efficiency of 80–90%. It is also shown that through the introduction of high aspect ratio pixel separating trenches, inter-pixel electrical crosstalk can be avoided.