On the Power Dissipation of Embedded Memory Blocks Used to Implement Logic in Field-Programmable Gate Arrays

Scott Y L Chin,Steven J E Wilton,Clarence S P Lee

doi:10.1155/2008/751863

Scott Y L Chin, Steven J E Wilton + Show 1 more

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https://doi.org/10.1155/2008/751863

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Abstract

We investigate the power and energy implications of using embedded FPGA memory blocks to implement logic. Previous studies have shown that this technique provides extremely dense implementations of some types of logic circuits, however, these previous studies did not evaluate the impact on power. In this paper, we measure the effects on power and energy as a function of three architectural parameters: the number of available memory blocks, the size of the memory blocks, and the flexibility of the memory blocks. We show that although embedded memories provide area efficient implementations of many circuits, this technique results in additional power consumption. We also show that blocks containing smaller-memory arrays are more power efficient than those containing large arrays, but for most array sizes, the memory blocks should be as flexible as possible. Finally, we show that by combining physical arrays into larger logical memories, and mapping logic in such a way that some physical arrays can be disabled on each access, can reduce the power consumption penalty. The results were obtained from place and routed circuits using standard experimental physical design tools and a detailed power model. Several results were also verified through current measurements on a 0.13 μm CMOS FPGA.

Highlights

On-chip user memory has become an essential and common component of field programmable gate arrays (FPGAs)
We would expect a decrease in the amount of logic that can be mapped to each memory array
We suggest that designers of future heterogeneous technology mapping algorithms should perform an evaluation of the power characteristics of their results, similar to the studies presented in this paper

Summary

Introduction

On-chip user memory has become an essential and common component of field programmable gate arrays (FPGAs). FPGAs are used to implement entire systems on a chip (SoC’s) rather than the small logic subcircuits that have traditionally been targeted to FPGAs. One of the key differences between these large systems and smaller logic subcircuits is that the large systems often require storage. Embedded FPGA memory array architectures can be described by three parameters: N, B, and weff. It is important to note that the shape of the physical array does not change as the chip is configured (it is fixed when the FPGA is manufactured). Note that the width of the physical array (the number of columns) must be at least as large as the largest value in weff so that weff bits can be read from the array in one access

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