On the Performance of Thermoelectric Energy Generators by Stacked Thermocouples Design in CMOS Process

Abstract

A semiconductor thermoelectric energy generator (TEG) with a stacked thermocouple design is developed to increase thermocouple density and achieve superior harvesting performance competitive to the BiTe-based TEGs. The stacked thermocouple design is by having the P-polysilicon layer above the N-polysilicon layer, such that the thermocouple has 1/2 footprint compared with the coplanar thermocouple design. For a TEG implemented by the standard complementary metal–oxide–semiconductor (CMOS) process [Taiwan Semiconductor Manufacturing Company (TSMC) 0.35- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> two polysilicon layers and four metal layers (2P4M)], the 64- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}\,\,\times $ </tex-math></inline-formula> 2- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> thermocouple of thickness 0.455 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> (0.275- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> P-thermoleg above 0.180- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> N-thermoleg) can achieve 0.084- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{W}$ </tex-math></inline-formula> /cm2K2 power factor and 9.136-V/cm2K voltage factor in analysis and 0.075 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{W}$ </tex-math></inline-formula> /cm2K2 and 7.004 V/cm2K in experiment. Both factors are about twice over those of the TEG with coplanar thermocouples, and they are significantly superior to all TEGs with polysilicon thermocouples. The TEG performance can be increased further by stacking more thermocouples and/or by adopting polysilicon layer(s) of higher Seebeck effect. For a TEG with one stacked thermocouple by the CMOS process [TSMC 0.18- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> one polysilicon layer and six metal layers (1P6M)], the polysilicon layer of higher thermoelectric conversion efficiency can achieve 0.476- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{W}$ </tex-math></inline-formula> /cm2K2 power factor and 60.811-V/cm2K voltage factor.