On the origin of the shunt effect in polycrystalline gallium arsenide pn-junction devices

Abstract

pn-Junction diodes have been fabricated on polycrystalline wafers by liquid phase epitaxy (LPE). The influence of grain boundaries on the current-voltage characteristics of the diodes has been investigated. It has been found that only a few grain boundaries shunt the junction. Grain boundary test devices have been fabricated on lightly Si-doped wafers as well as on LPE-grown n-type (Sn) and p-type (Zn) layers. Highly rectifying grain boundaries with remarkably high barrier height values exceeding 1 V have been detected in the Si-doped wafers. The grain boundaries in the grown layers generally showed ohmic characteristics. The barrier height and the concentration of mobile carriers at gallium arsenide grain boundaries have been calculated from the balance of charge. The calculation performed is not restricted to the case of depletion but also applies to inversion. The calculation shows the presence of inversion paths along grain boundaries in lightly n-type material. These inversion paths are believed to be at least partly responsible for the shunt effects observed at some polycrystalline junction devices. Device structures designed to block the shunting path are proposed.