Abstract
This work presents a new design methodology for inductively-degenerated cascode low-noise amplifiers using advanced epitaxial-base SiGe HBTs. IIP3 and noise figure are simulated using a calibrated linear circuit analysis and Volterra series methodology as a function of the two major design variables: emitter geometry and biasing current. Analytical IIP3 expressions with/without the CB capacitance are derived and used to explain the numerical simulation results. The cancellation among individual non-linearities is maximized at a certain I C and emitter length combination, thus producing an IIP3 peak. The analytical expressions are in good agreement with the numerical simulation results, and can be used for robust circuit design.
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