On the Non-Data-Aided Maximum Likelihood Phase Error Detectors for 16- and 32-APSK

Abstract

The non-data aided maximum likelihood phase error detectors (PEDs) for use in phase-lock loops (PLLs) for 16-APSK and 32-APSK are derived and analyzed. The derivation focuses on a numerically stable expression for the PED output as a function of the derotated matched filter input. The analysis focuses on the S-curve, phase ambiguity, and phase error variance. The 16-APSK PED S-curve exhibits 12 lock points (a twelve-fold phase ambiguity) and, when used in a PLL, produces a phase error variance better than commonly used alternatives and achieves its theoretical lower bound at a lower signal-to-noise ratio than the alternatives. The 32-APSK PED S-curve exhibits 16 (low signal-to-noise ratio) or 20 (high signal-to-noise ratio) lock points (a 16- or 20-fold phase ambiguity) and, when used in a PLL, produces a phase error variance better than commonly used alternatives and achieves its theoretical lower bound at a lower signal-to-noise ratio than the alternatives. It is proved that the two PEDs converge to their corresponding decision-directed PEDs as signal-to-noise ratio increases.