Abstract
Delamination fracture of positive temperature coefficient PTC thermistors is a mode of thermal shock failure which manifests itself by cracking of the ceramic along a plane approximately parallel to the electrodes. This mode of failure is observed in high-power switching applications. It results from the build-up of thermal stresses whose amplitude is governed by a large number of geometrical, electrical and thermomechanical parameters. An experimental procedure is proposed for the quantitative evaluation of the thermal shock resistance of PTC thermistors. This resistance is characterized by a 'fracture voltage' defined as the voltage causing an increase by more than 10% of the room-temperature resistance after less than 25 switching cycles. The crack trajectory during the successive cycles is revealed by microscopic observation of the fracture surfaces. These experimental results are interpreted by comparison with the temperature and stress distributions computed using a newly developed three dimensional model. This modelling allows evaluation of the relative importance of the parameters affecting failure. The cracking mechanism can be partly elucidated on the basis of the computations of the maps of the normal stresses arising in homogeneous and non-homogeneous ceramics.
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